SOCC 2020 Tutorial Day Program

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September 8, 2020

 Track A - Virtual Room 1 - Session Chair: Selçuk Köse

TA1

Energy-Efficient Memory-Centric Accelerator Design for Mobile/Edge-based AI Inference
Prof. Po-Tsang Huang, National Chiao Tung University, Taiwan

Abstract: Deep convolutional neural networks (CNNs) are widely used in feature classification, recommender systems and image recognition. Nevertheless, deep CNNs are difficult to be fully deployed to edge/mobile/IoT devices because of both memory-intensive and computation-intensive workloads. The energy efficiency of CNNs is dominated by convolution computation and off-chip memory (DRAM) accesses, especially for DRAM accesses. In this tutorial, we will outline the important bottlenecks and solutions for energy-efficient computing hardware of mobile/edge-based AI inference, notably the end of Moore’s Law and the memory wall problem. We will then discuss several memory-centric accelerator design approaches and interconnection architectures using advanced technologies, including TSV 3D-SRAM, 3D-DRAM, monolithic 3D-SRAM and computation-in-memory circuits.

Biography: Po-Tsang Huang received the B.Sc., M.Sc., and Ph.D. degrees from the Department of Electronics Engineering, National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 2002, 2004, and 2010, respectively. From 2011 to 2014, he was an assistant research fellow at NCTU. From 2015 to 2016, he was an associate research fellow at NCTU and a visiting scholar at University of California, Los Angeles (UCLA). Currently, he is an assistant professor at International College of Semiconductor Technology, NCTU. His research interests focus on low-power digital IC design, hardware design for AI and machine learning applications, embedded memory design, low-power TSV 2.5D/3D integration, monolithic 3DIC and low-power SoC/SiP designs with particular emphasis on inter-chip/intra-chip data communications & memory sub-systems.

TA2

Efficient Power Design for IoT/IIoT & 5G Applications
Brian Zahnstecher, Principal, PowerRox LLC, USA

Abstract: In general, the success of any electronics deployment is dependent on the effective design and implementation of its power electronics. When it comes to battery-operated devices or other things in the Internet of Things (IoT) / Industrial IoT (IIoT), a highly-efficient design must be realized to optimize energy consumption for various reasons, whether it be to preserve battery life, enable a smaller form-factor, or even be the difference between the ability to viably deploy the application or not. As we move into the 5G era and anticipate the deployment of many billions or even a trillion devices, this focus is of critical importance at all levels of deployment from the tiniest systems to the largest networks. The tutorial will cover above issues.

Biography: Brian Zahnstecher is a Sr. Member of the IEEE, Chair (Emeritus) of the IEEE SFBAC Power ElectronicsSociety (PELS) awarded 2017 Best Chapter awards at the local/national/worldwide levels concurrently (an unprecedented achievement), sits on the Power Sources Manufacturers Association (PSMA) Board of Directors, is Co-founder & Co-chair of the PSMA Reliability Committee, Co-chair of the PSMA Energy Harvesting Committee, and is the Principal of PowerRox, where he focuses on power design, integration, system applications, OEM market penetration, market research/analysis, and private seminars for power electronics. He Co-chairs the IEEE Future Directions (formerly 5G) Initiative webinar series and is the founding Co-chair of the IEEE 5G Roadmap Energy Efficiency Working Group, authored the Group’s position paper, and has lectured on this topic at major industry conferences. He has successfully handled assignments in system design/architecting, AC/DC front-end power, EMC/EMI design/debug, embedded solutions, processor power, and digital power solutions for a variety of clients. He previously held positions in power electronics with industry leaders Emerson Network Power (now Advanced Energy), Cisco, and Hewlett-Packard, where he advised on best practices, oversaw product development, managed international teams, created/enhanced optimal workflows and test procedures, and designed and optimized voltage regulators. He has been a regular contributor to the industry as an invited keynote speaker, author, workshop participant, session host, roundtable moderator, and volunteer. He has over 15 years of industry experience and holds Master of Engineering and Bachelor of Science degrees from Worcester Polytechnic Institute.

Track B - Virtual Room 2 - Session Chair: Lan-Da Van

TB1

Annealing Processing and Emerging Non-volatile Memory for AI Chips
Prof. Takayuki Kawahara, Tokyo University of Science, Japan

Abstract: First, the importance of processing on the edge is outlined. This is followed by a discussion of neural networks and deep learning as part of the development trends of AI chips, after which the incorporation of learning functions, sparseness, and accuracy of calculation is discussed. Next, it moves on to discuss the development trends of emerging nonvolatile memories, especially STT-RAM and SOT-RAM, that are vital for low power consumption and examples of applications to AI. Finally, the development of the fully-coupled-spin annealing AI chip that helps solve combinatorial optimization problems is disclosed. This represents a new paradigm in edge computing.

Biography: Takayuki Kawahara received B.S. and M.S. degrees in Physics and a Ph.D. degree in Electronics from Kyushu University, Fukuoka, Japan in 1983, 1985, and 1993. From 1997 to 1998, he was a visiting researcher at the Electronics Laboratory (LEG) in the Swiss Federal Institute of Technology, Lausanne (EPFL). Since joining the Central Research Laboratory (CRL), Hitachi Ltd. in 1985, he has made fundamental contributions in the field of low-power memories. In the DRAM area, he initiated subthreshold-current reduction by gate-source self-reverse biasing in 1993. He also pioneered the charge-recycling scheme, which is now widely applied in various circuits. In flash memory, he and his team developed a 128-Mb chip. He also reported the world’s first fully functional 2-Mb STT-RAM proto chip in 2007, and his team developed FD-SOI SRAM circuitry with back-gate control. After leaving CRL as a Chief Researcher, in 2014, he became a professor in the Department of Electrical Engineering at the Tokyo University of Science. The main focus of his laboratory is sustainable electronics. His research group carries out cutting-edge research on ultra-low-power artificial intelligence (AI) devices and circuits, sensor and AI signal processing, and spin-current applications.

He was an IEEE SSCS distinguished lecturer in 2008/2009 and the FE regional chair of IEEE ISSCC 2009/2010. He is a recipient of the 9th (2009) Yamazaki-Teiichi Prize, the 2014 IEICE Electronics Society Award, and the Prize for Science and Technology (Development Category) in the FY2017 Commendation for Science and Technology by the Minister of Education, Culture, Sports, Science and Technology. He is also an IEEE Fellow.

TB2

Portable and Scalable High Voltage Circuits for Automotive Applications in BiCMOS Processes
Dr. Sri Navaneeth Easwaran, Texas Instruments Inc, USA.

Abstract: Systems-On-Chip (SoC) are increasing in automotive applications like airbag, braking, power steering, and motor drivers. Automotive ICs are similar to conventional analog circuits used in consumer electronics, but they have to handle a wide range of input voltage (5V to 40V) and currents (30mA to 4A) and withstand -18V levels. This tutorial introduces the SoC requirements, design of high side and low side drivers, R-L-C loads, thermal and electrical Safe Operating Area, diagnostics, transceivers, biasing techniques to ensure correct turn ON/OFF behavior, and parasitic bipolars. Finally, the tutorial presents the scalability and programmability of these designs.

Biography: Dr.–Ing. Sri Navaneeth Easwaran was born in Erode, India on October 19, 1977. He received his Bachelor of Engineering, B.E. Degree (cum laude) in Electronics and  Communication Engineering from Bharathidasan University, India), in 1998. He worked at SPIC Electronics and STMicroelectronics, India between 1998 and 2000. From 2000 he worked for Philips Semiconductors at Bengaluru India, Zurich, Switzerland and Nijmegen, The Netherlands where he designed analog circuits for Mobile Baseband and Power Management Units. While working at Philips Semiconductors, he also received his International M.Sc. degree in Electrical Engineering from the University of Twente, Enschede (Prof. Dr.ir. Bram Nauta’s ICD group), The Netherlands on the design of NMOS LDOs.
From 2006 he started his work at Texas Instruments GmbH Freising, Germany and he joined the Technische Elektronik group at Friedrich-Alexander-Universität Erlangen-Nürnberg in January 2010 as an external Ph.D student under the supervision of Prof. Dr. –Ing. Dr. -Ing. habil. Robert Weigel. His research focused on the fault tolerant design of smart power drivers and diagnostic circuits. He received his Dr.-Ing degree from Friedrich-Alexander-Universität Erlangen-Nürnberg in May, 2017.
Since September 2010 he is with Texas Instruments Inc, Dallas, Texas USA where he has the design lead for several airbag squib driver ICs. He has also designed analog high voltage, negative voltage tolerant circuits for automotive power steering and braking ICs. He was elected as the Senior Member of IEEE in 2011, Member Group Technical Staff at in 2014 and Senior Member Technical Staff in 2019 at Texas Instruments. He has more than 20 patents (US and German) in the field of Analog Mixed Signal IC Design and has 19 ISO26262, IEEE Journal and conference publications.