September 8-11, 2020

Keynote Speaker
Wednesday, Sep. 9, 2020, 10:20 - 11:05 EDT

Jered Floyd
Member of Technical Staff, Technology Strategist
Red Hat, Inc.

Edge Computing Drives SoC Open Software Platforms”

Floyd1Part of Red Hat's Office of the CTO, Jered Floyd helps define technology strategy at the intersection of emerging trends and Red Hat's enterprise businesses. His current focus is on using edge computing to extend the open hybrid cloud to locations beyond the data center, enabling new, distributed applications on top of Red Hat's trusted platforms.


Abstract: Edge computing architectures extend enterprise applications broadly beyond the data center and cloud, including smaller environments that are the traditional domain of embedded systems.  This, in turn, changes the requirements for these platforms, often built around custom or semi-custom Systems-on-Chip.  Embedded solutions become device edge (or “far edge”) systems that are ubiquitously connected to the outside world, bringing the expectation of stronger security attestation, standardization of software and interfaces, and simplification of the development environment.

Keynote Speaker
Wednesday, Sep. 9, 2020, 11:10 - 11:55 EDT

Serge Leef
Program Manager
Microsystems Technology Office, DARPA

Incorporation of Security into Chip Design Methodologies”


Serge Leef joined DARPA in August 2018 as a program manager in the Microsystems Technology Office (MTO). His research interests include computer architecture, simulation, synthesis, semiconductor intellectual property (IP), cyber-physical modeling, distributed systems, secure design flows, and supply chain management. He is also interested in the facilitation of startup ecosystems and business aspects of technology. He came to DARPA from Mentor, a Siemens Business where from 2010 until 2018 he was a Vice President of New Ventures, responsible for identifying and developing technology and business opportunities in systems-oriented markets. Additionally, from 1999 to 2018, he served as a division General Manager, responsible for defining strategies and building successful businesses around design automation products in the areas of hardware/software co-design, multi-physics simulation, IP integration, SoC optimization, design data management, automotive/aerospace networking, cloud-based electronic design, Internet of Things (IoT) infrastructure, and hardware cybersecurity. Prior to joining Mentor, he was responsible for design automation at Silicon Graphics, where he and his team created revolutionary, high-speed simulation tools to enable the design of high-speed 3D graphics chips, which defined the state-of-the-art in visualization, imaging, gaming, and special effects for a decade. Prior to that, he managed a CAE/CAD organization at Microchip and developed functional and physical design and verification tools for major 8- and 16-bit microcontroller and microprocessor programs at Intel. Leef received his Bachelor of Science degree in electrical engineering and Master of Science degree in computer science from Arizona State University. He has served on corporate, state, and academic advisory boards, delivered numerous public speeches, and holds two patents.

Abstract: Incorporation of security into modern chips is frequently viewed as a burden with unclear economic benefits. Absence of automation makes incorporation of security a laborious, manual task that requires very specific domain expertise not widely available in the semiconductor or system companies. Emerging security design and verification tool technologies are starting to show promise. Additionally, novel design flows can offer protection from known attack strategies by streamlining inclusion of scalable defense mechanisms in a way that maximizes architectural exploration of security vs. economics trade-offs.

Keynote Speaker
Thursday, Sep. 10, 2020, 10:10 - 10:55 EDT

Song Han
Assistant Professor

Tiny Machine Learning on Microcontrollers”


Song Han is an assistant professor in MIT’s Department of Electrical Engineering and Computer Science. He received his PhD degree from Stanford University. His research focuses on efficient deep learning computing. He proposed “deep compression” technique that can reduce neural network size by an order of magnitude without losing accuracy, and the hardware implementation “efficient inference engine” that first exploited pruning and weight sparsity in deep learning accelerators. His recent work on hardware-aware neural architecture search was highlighted by MIT News, Qualcomm News, VentureBeat, IEEE Spectrum, integrated in PyTorch and AutoGluon, and received many low-power computer vision contest awards in flagship AI conferences (CVPR’19, ICCV’19 and NeurIPS’19). Song received Best Paper awards at ICLR’16 and FPGA’17, Amazon Machine Learning Research Award, SONY Faculty Award, Facebook Faculty Award. Song was named “35 Innovators Under 35” by MIT Technology Review for his contribution on “deep compression” technique that “lets powerful artificial intelligence (AI) programs run more efficiently on low-power mobile devices.” Song received the NSF CAREER Award for “efficient algorithms and hardware for accelerated machine learning.”

Abstract: Machine learning on tiny IoT devices based on microcontroller units (MCU) is appealing but challenging: the memory of microcontrollers is 2-3 orders of magnitude less even than mobile phones, not to mention GPUs. We propose MCUNet, a framework that jointly designs the efficient neural architecture (TinyNAS) and the lightweight inference engine (TinyEngine). MCUNet enables ImageNet-scale inference on microcontrollers that has only 1MB of FLASH and 320KB SRAM, which used to require tens or hundreds of megabytes. It achieves significant speedup compared to TF-Lite Micro, CMSIS-NN, and MicroTVM. Our study suggests that the era of tiny machine learning on IoT devices has arrived.

Keynote Speaker
Thursday, Sep. 10, 2020, 11:05 - 11:50 EDT

Diana Marculescu
Professor, Motorola Regents Chair in Electrical and Computer Engineering,
Cockrell Family Chair for Departmental Leadership
University of Texas, Austin

miliJoules for 1000 Inferences: Machine Learning Systems 'on the Cheap'


Diana Marculescu is Department Chair, Cockrell Family Chair for Engineering Leadership #5, and Professor, Motorola Regents Chair in Electrical and Computer Engineering #2, at the University of Texas at Austin. Before joining UT Austin in December 2019, she was the David Edward Schramm Professor of Electrical and Computer Engineering, the Founding Director of the College of Engineering Center for Faculty Success (2015-2019) and has served as Associate Department Head for Academic Affairs in Electrical and Computer Engineering (2014-2018), all at Carnegie Mellon University. She received the Dipl.Ing. degree in computer science from the Polytechnic University of Bucharest, Bucharest, Romania (1991), and the Ph.D. degree in computer engineering from the University of Southern California, Los Angeles, CA (1998). Her research interests include energy- and reliability-aware computing, hardware aware machine learning, and computing for sustainability and natural science applications. Diana was a recipient of the National Science Foundation Faculty Career Award (2000-2004), the ACM SIGDA Technical Leadership Award (2003), the Carnegie Institute of Technology George Tallman Ladd Research Award (2004), and several best paper awards. She was an IEEE Circuits and Systems Society Distinguished Lecturer (2004-2005) and the Chair of the Association for Computing Machinery (ACM) Special Interest Group on Design Automation (2005-2009). Diana chaired several conferences and symposia in her area and is currently an Associate Editor for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. She was selected as an ELATE Fellow (2013-2014), and is the recipient of an Australian Research Council Future Fellowship (2013-2017), the Marie R. Pistilli Women in EDA Achievement Award (2014), and the Barbara Lazarus Award from Carnegie Mellon University (2018). Diana is a Fellow of ACM and IEEE.

Abstract: Machine learning (ML) applications have entered and impacted our lives unlike any other technology advance from the recent past. While the holy grail for judging the quality of a ML model has largely been serving accuracy, and only recently its resource usage, neither of these metrics translate directly to energy efficiency, runtime, or mobile device battery lifetime. This talk uncovers the need for designing efficient convolutional neural networks (CNNs) for deep learning mobile applications that operate under stringent energy and latency constraints. We show that, while CNN model quantization and pruning are effective tools in bringing down the model size and resulting energy cost by up to 1000x while maintaining baseline accuracy, the interplay between bitwidth, channel count, and CNN memory footprint uncovers a non-trivial trade-off.  Surprisingly, there exists a single weight bitwidth that is superior to others for a given storage constraint, even outperforming mixed-precision quantization.  Furthermore, our results show that when the channel count is allowed to change, a single weight bitwidth can be sufficient for model compression, which greatly reduces the software and hardware optimization costs for CNN-based ML systems.

Keynote Speaker
Friday, Sep. 11, 2020, 10:10 - 10:55 EDT

Christy Tyberg
Senior Manager, Quantum Hardware Technology Development
IBM Quantum, IBM T.J. Watson Research Center

"Quantum Systems -  The foundation for a new model of computation"


Christy Tyberg is a Principal Research Staff Member and Senior Manager for Quantum Hardware Technology Development at IBM Quantum. Her team is responsible for fabricating current and future IBM Quantum hardware, and developing new materials and processes to improve hardware performance. Prior to joining the IBM Quantum team, she served as Technical Program Manager for 3D Systems Research focused on development and evaluation of 3D chip stacking technology. She has also held other technical and management positions at IBM Research in the area of CMOS BEOL technology development. Prior to joining IBM Research, Christy received her PhD in Polymer Chemistry from Virginia Tech. She has authored a number of technical publications and holds over 35 patents.

 Abstract:  Quantum computing, once considered a theoretical concept, has in recent years moved from laboratory experiments to public accessibility via the cloud. Quantum computing uses the same physical rules that atoms follow to manipulate information. At this very fundamental level, quantum computers execute quantum circuits much like a computer executes logic circuits, but by using the physical phenomena of superposition, entanglement, and interference to implement mathematical calculations that are out of the reach of even the most advanced supercomputers. In this talk I will give an overview of the IBM Quantum effort, where we are working to increase device performance of our core superconducting qubit systems. We are in an exciting era of laying the foundation for a new computing paradigm, through cutting edge research in quantum hardware and systems.

Keynote Speaker
Friday, Sep. 11, 2020, 11:05 - 11:50 EDT

Norman Chang
Ansys Fellow & Chief Technologist

ML-augmented Thermal Solution from Architecture to Layout for Large SoC and 3DIC


Norman Chang co-founded Apache Design Solutions in February 2001 and currently serve as Ansys Fellow and Chief Technologist at Semiconductor BU, ANSYS, Inc. He has been leading the AI/ML application effort since 2017 at ANSYS. Dr. Chang received his Ph.D. in Electrical Engineering and Computer Sciences from University of California, Berkeley. He holds eighteen patents and has authored over 50 technical papers. He is currently in the committee for ESDA-EDA and Si2 AI/ML TAB.

Abstract: With the emergence of complicated 3DIC designs for AI/5G/HPC/SiPh applications, comprehensive thermal solution is needed from architecture to layout stages of the design. This is due to the need of fast early consideration on the impact of logic partition, TSV placement, logic/memory chip proximity under different workload. Both thermal and thermal-induced stress would need to be considered for the 3DIC design during analysis stage with ML-augmented hierarchical thermal simulation. An application of running thermal analysis on a 3DIC design with Interposer-based architecture will be illustrated.


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