Tuesday Sept. 8, 2020:  10AM – 1PM EDT
Session Chair: Thanh Tran, Rice University

Talk 1:

High-Speed Electrical I/O Interfaces and Interconnects from 56 Gbps to 112Gbps and Beyond
Dr. Peng Mike Li, Intel Fellow

Abstract: This presentation reviews the challenges that high-speed electrical I/O interfaces and interconnects face, from 56 Gbps to 112 Gbps, including modulation format, transmitter and receiver architectures and circuits, channel loss/crosstalk characteristics and topologies, and then discuss how those challenges had been solved. Scalability and extendibility from 112 Gbps I/O to next generation I/O (e.g., 2X in speed) will also be discussed.      

Biography: Dr. Peng (Mike) Li is an Intel Fellow and the technologist for high-speed I/O and interconnects at Intel Corporation. He serves as Intel’s technical expert and adviser in high-speed I/O and link technology; standards; SerDes architecture; electrical and optical signaling and interconnects; silicon photonics integration; optical field-programmable gate arrays (OFPGAs); and high-speed simulation, debug and test for jitter, noise, signaling and power integrity, from deign validation, to high-volume manufacturing (HVM).
Li joined Intel in 2015 with the acquisition of Altera Corp., where he had held a similar role since 2012. Before joining Altera in 2007, Li spent nearly a decade at Wavecrest Corp., culminating in his seven-year tenure as chief technology officer (CTO). He began his career in 1991 as a post-doctorate researcher at the Space Sciences Laboratory at the University of California, Berkeley.
A distinguished scientist and technologist, Li has contributed extensively to industry standards during his career, including PCI Express, Ethernet, Optical Internetworking Forum (OIF), Fibre Channel, and Serial ATA. He has also published widely, including >110 referred papers, >40 patents, five books and book chapters on jitter and high-speed architecture, testing, modeling, and analysis.
Li earned a bachelor’s degree in space physics from the University of Science and Technology of China in Hefei, China; a master’s degree in physics and a master’s degree in electrical and computer engineering, both from the University of Alabama in Huntsville (UAH); and a Ph.D. in physics, also from UAH. Li was named an IEEE Fellow in 2012, an Intel Fellow in 2015, and Engineer of the year (2018, Designcon). He has been elected as an affiliated professor at the Department of Electrical Engineering, University of Washington, Seattle, since 2010.

Talk 2:

Versal-ACAP Architecture, Programming, Machine Learning and 5G
Dr. Chris Dick, Xilinx Fellow/DSP Chief Architect

Abstract: This presentation will provide an overview of one of the new generation of 7nm devices from Xilinx, the Versal ACAP multi-core vector processor. The overall device architecture together with a detailed description of the Vector processor datapath will be presented. The ASIC on-chip Network-on-Chip (NoC), DDR memory controllers an other silicon structures that support dataflow with the chip will be reviewed. The programming model for the device will be described along with some application use cases for machine learning inference and 4G/5G wireless radio will be covered.

Biography: Dr Chris Dick is a Xilinx fellow and manages the machine learning applications team at Xilinx. His research and product development background is in the area of real-time signal processing with a particular emphasis on 4G and 5G wireless systems. During his tenure at Xilinx he initiated the Xilinx wireless baseband and radio R\&D programs. His current focus is on the Xilinx 7nm Versal ACAP VLIW multi-processor technology. For the past 3 years he has been working in the area of machine learning with a particular emphasis on using the Versal architecture for machine learning inference workloads. He has over 200 publications, 70 patents and is an adjunct professor at Rice University and Santa Clara University in Silicon Valley where he teaches a class on machine learning using FPGAs Together with Rice University colleagues he was awarded the 2018 IEEE Communications Award for Advances in Communication.

Talk 3:

High-Speed Signal Integrity Challenges and Opportunities for Next Generation Technologies
Dr. Bhyrav Mutnury, Senior Distinguished Engineer and Global Team Lead, Dell EMC

Abstract: The challenges associated with high-speed signal integrity (SI) are becoming exponentially complex with the doubling of signal speeds every generation. In this presentation, high-speed server design is used an example to demonstrate the next generation SI challenges and potential opportunities to overcome these challenges. The presentation covers basics of SI, high-speed interconnects, analog and digital equalization and high-speed challenges beyond 32 Gbps.

Biography: Dr. Bhyrav Mutnury is a Senior Distinguished Engineer and Global Team Lead at Enterprise Signal Integrity group at Dell EMC, where he is responsible for storage, network, rack and blade server designs. Dr. Mutnury is driving the next generation high speed interfaces and modeling methodologies at Dell. His innovative design of experiments-based methodologies and integrated tool suite to model high speed SerDes for electrical and physical designs has provided 100X improvement on the productivity. He is the electrical interface expert on GbE, XAUI, FC, IB, USB, PCIe, UPI, XGMI, DDR and SAS. He has more than 18 years of progressive experience in system design with strong focus on electrical modeling, analysis and optimization of complex high-speed servers. The research pioneered by Dr. Mutnury not only resulted in faster design spins of complex servers but also resulted in cost savings in designs without trading off signal integrity robustness. Dr. Mutnury was involved in numerous research projects with Georgia Institute of Technology, Missouri Institute of Science and Technology, Penn State University, Indian Institute of Sciences (IISc) and National Taiwan University (NTU).
He received his Master of Science degree in Electrical Engineering in 2002 and Doctor of Philosophy degree in Electrical Engineering in 2005 from the Georgia Institute of Technology, Atlanta, GA.
Dr. Mutnury has authored and co-authored more than 75 refereed publications in various IEEE and non-IEEE conferences. These publications covered various disciplines including package and interconnect modeling, analysis and optimization; active circuit and transistor level circuit macromodeling; high speed serial and multidrop interface design, modeling and optimization. Dr. Mutnury has 150 issued patents and another 60 more filed in the fields of electrical cable design, package and printed circuit board design and optimization, and electrical design space exploration using evolutionary techniques. He is currently a senior member of Institute of Electrical and Electronic Engineers (IEEE).

Talk 4:

Challenges and Solutions for High-Bandwidth Density, Energy-Efficient, Short-Reach Signaling that Enables Massively Scalable Parallelism
Dr. John Wilson, Nvidia Research, Durham, NC

Abstract:
 We are just now entering the era of massive parallel processing, where computing for Deep Learning, Artificial Intelligence, & Big Data will scale for decades. To make these systems feasible, we must optimize the entire system and understand that the energy-cost of communication is a tax on real performance. In this talk, I’ll cover the challenges and solutions that enable Tera-Byte/s communication for on- & off-chip links, including: packaging limitations, signaling integrity, and the design of energy-efficient high-speed links. I’ll discuss the benefits Ground Referenced Signaling for short-reach links and how it is applicable to communication over silicon interposers, organic packages, and PCBs. Then, I’ll discuss on-chip communication using Balanced Charge-Recycling Signaling as the final branch in connecting short-reach systems.

Biography: John Wilson joined Nvidia in 2012 as a Senior Research Scientist in the Circuits Research Group. Recently, he led a team in the design of a 25Gbps Single-Ended Ground Referenced Signaling link, in 16nm FinFET CMOS, enabling Tera-Byte per-second communication for on-package and off-package channels at 1.17pJ/bit. He received the BS, MS, & Ph.D. degrees in Electrical Engineering from North Carolina State University. His interests include: high-speed I/O circuit design, on-chip signaling, signal integrity, advanced packaging, and chip/package co-design. From 2003-2006 he was a Research Professor at NCSU leading projects in advanced packaging, low-power capacitive & inductive coupled transceivers for 3D-ICs, and circuits for on-chip global signaling. From 2006-2012, while with Rambus, Inc. in Chapel Hill, NC, he worked on high-speed I/O circuit design, and methods to mitigate signal & power integrity problems in memory interfaces.